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Winbond ExpressCardTM Power Interface Switch W83L351 Series
W83L351 Series
W83L351 Series Data Sheet Revision History
NO PAGES DATES VERSION VERSION ON WEB MAIN CONTENTS
1. 2 3 4 5 6 7
All 28
Apr. /07 July 5, 2007
1.0 1.1
N.A
All versions before 1.0 are preliminary versions. Update the ordering information and add the taping spec.
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
Table of Contents1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. FEATURES ................................................................................................................................. 1 PIN CONFIGURATION AND DESCRIPTION ............................................................................ 2 APPLICATION CIRCUIT............................................................................................................. 5 INTERNAL BLOCK DIAGRAM ................................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ............................................................................................. 7 RECOMMENDED OPERATING CONDITIONS ......................................................................... 8 ELECTRICAL CHARACTERISTICS........................................................................................... 9 SWITCHING CHARACTERISTICS .......................................................................................... 12 FUNCTIONAL TRUTH TABLES ............................................................................................... 13 TYPICAL OPERATING WAVEFORMS .................................................................................... 15 EXPRESSCARD TIMING DIAGRAMS ..................................................................................... 20 PACKAGE DIMENSION ........................................................................................................... 24 ORDERING INFORMATION .................................................................................................... 28 TOP MARKING SPECIFICATION ............................................................................................ 29
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W83L351 Series
1. FEATURES
* * * * * * * * * Meets the ExpressCardTM Standard (ExpressCard|34 or ExpressCard|54) Compliant with the ExpressCardTM Compliance Checklists ExpressCard Compliance ID: EC100098 (W83L351G), EC100115 (W83L351YG/YCG) Fully Satisfies the ExpressCardTM Implementation Guidelines Supports System with WAKE Function TTL-Logic Compatible Inputs Short Circuit and Thermal Protection 0 to 70 Ambient Operating Temperature Range Available in a 20-pin TSSOP or a 20-pin QFN
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
2. PIN CONFIGURATION AND DESCRIPTION
RCLKEN 18
SHDN# 20
AUXIN 17
SYSRST# SHDN# STBY# 3.3VIN 3.3VIN 3.3VOUT 3.3VOUT PERST# NC
1 2 3 4 5 6 7 8 9
20 OC# 19 RCLKEN 18 AUXIN 17 AUXOUT 16 1.5VIN 15 1.5VIN 14 1.5VOUT 13 1.5VOUT 12 CPPE# 11 CPUSB# STBY# 3.3VIN 3.3VOUT NC NC 1 2 3 4 5
OC# 19
NC 16 15 14 13 12 11 10 CPPE# AUXOUT NC NC 1.5VIN 1.5VOUT
GND 10
6 SYSRST#
7 GND
8 PERST#
9 CPUSB#
W83L351G (Top View)
W83L351YG W83L351YCG (Top View)
PIN SYMBOL G YG YCG I/O FUNCTION
SYSRST#
1
6
I(*)
System Reset input - active low, logic level signal. Internally pulled up to AUXIN. This input is driven by the host system and directly affects PERST#. Asserting SYSRST# (logic low) forces PERST# to assert. RCLKEN is not affected by the assertion of SYSRST#. Shutdown input - active low, logic level signal. Internally pulled up to AUXIN. When asserted (logic low), this input instructs the power switch to turn off all voltage outputs and the discharge FETs are activated.
SHDN#
2
20
I(*)
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W83L351 Series
Continued
PIN SYMBOL G YG YCG I/O FUNCTION
STBY#
3
1
I(*)
Standby input - active low, logic level signal. Internally pulled up to AUXIN. When asserted (logic low) after the card is inserted, this input places the power switch in standby mode by turning off the 3.3V and 1.5V power switches and keeping the AUX switch on. If the signal is asserted prior to the card being present, STBY# places the power switch in OFF Mode by turning off the AUX, 3.3V, and 1.5V power switches. A logic level power good (with delay). When powered up, this output remains asserted (logic level low) until all power rails are within the tolerance. Once all power rails are within the tolerance and RCLKEN has been released (logic high), PERST# is deasserted (logic high) after a time delay, as shown in the parametric table. When powered down, this output is asserted whenever any of the power rails drops below their voltage tolerance. The PERST# signal is an output from the host system and an input to the ExpressCard module. This signal is only used by PCI Express-based modules and its function is to place the ExpressCard module in a reset state.
PERST#
8
8
O
During power up, power down, or whenever power to the ExpressCard module is not stable or not within voltage tolerance limits, the ExpressCard standard requires that PERST# be asserted. As a result, this signal also serves as a power-good indicator to the ExpressCard module, and the relationship between the power rails and PERST# are explicitly defined in the ExpressCard standard. The host can also place the ExpressCard module in a reset state by asserting a system reset SYSRST#. This system reset generates a PERST# signal to the ExpressCard module without disrupting the voltage rails. This is normally called a warm reset. However, in a cold start situation, the system reset can also be used to prolong the assertion time of PERST#.
CPUSB#
11
9
I
(*)
Card Present input for USB cards. Internally pulled up to AUXIN. A logic low level on this input indicates that the card present supports the USB functions. When a card is inserted, CPUSB# is physically connected to ground if the card supports USB functions. Card Present input for PCI Express cards. Internally pulled up to AUXIN. A logic low level on this input indicates that the card present supports the PCI Express functions. When a card is inserted, CPPE# is physically connected to ground if the card supports PCI Express functions.
CPPE#
12
10
I(*)
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
Continued
PIN SYMBOL G YG YCG I/O FUNCTION
RCLKEN
19
18
Reference Clock Enable signal. As an output, it is a logic level power good to the host (no delay - open drain). As an input, if the signal is kept inactive (low) by the host, PERST# will be prevented from being de-asserted. Internally pulled up to AUXIN. This pin serves both as an input and an output. When powered up, a discharge FET keeps this signal at a low state as long as any of the output power rails is out of their tolerance range. Once all output power rails are within the tolerance, the switch releases RCLKEN, (*) I /O allowing it to transit to a high state (internally pulled up to AUXIN). The transition of RCLKEN from a low to a high state starts an internal timer for the purpose of de-asserting PERST#. As an input, RCLKEN can be kept low to delay the start of the PERST# internal timer. Because RCLKEN is internally connected to a discharge FET, this pin can only be driven low and should never be driven high as a logic input. When an external circuit drives this pin low, RCLKEN becomes an input; otherwise, this pin is an output. Over current status output (open drain). This pin is an open-drain output. When any of the three power switches (AUX, 3.3V, and 1.5V) is in an over current condition, OC# is asserted (logic low) by an internal discharge FET with a deglitch delay. Otherwise, the discharge FET is open, and the pin can be pulled up to a power supply through an external resistor. Primary voltage source, 3.3V input for 3.3VOUT Secondary voltage source, 1.5V input for 1.5VOUT Auxiliary voltage source, AUX input for AUXOUT and chip power. Switched output that delivers 0V, 3.3V or high impedance to the card. Switched output that delivers 0V, 1.5V or high impedance to the card. Switched output that delivers 0V, AUX or high impedance to the card. Ground No connection
OC#
20
19
OD
3.3VIN 1.5VIN AUXIN 3.3VOUT 1.5VOUT AUXOUT GND NC
4, 5 15,16 18 6, 7 13, 14 17 10 9
2 12 17 3 11 15 7 4, 5, 13, 14, 16
I I I O O O
Notice: (*) Be aware that no input pins can be driven HIGH before the Auxiliary voltage is VALID.
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W83L351 Series
3. APPLICATION CIRCUIT
AUXIN AUXOUT
C1 0.1U
C2 4.7U
C3 0.1U
C4 22U U1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 R1 2K AUXIN AUXOUT 1.5VIN 1.5VOUT CPPE# CPUSB# AUXIN RCLKEN
3.3VIN
3.3VOUT
SY SRST# SHDN# STBY # 3.3VIN 3.3VOUT PERST#
C5 0.1U
C6 4.7U
C7 0.1U
C8 22U
SY SRST# SHDN# STBY # 3.3VIN 3.3VIN 3.3VOUT 3.3VOUT PERST# NC GND
OC# RCLKEN AUXIN AUXOUT 1.5VIN 1.5VIN 1.5VOUT 1.5VOUT CPPE# CPUSB# W83L351G
1.5VIN
1.5VOUT
C9 0.1U
C10 4.7U
C11 0.1U
C12 22U
AUXIN
R1 2K AUXIN AUXOUT RCLKEN SHDN# 20 19 18 17 AUXIN 16 NC U1
C1 0.1U
C2 4.7U
C3 0.1U
C4 22U
SHDN#
OC#
3.3VIN
3.3VOUT STBY # C5 0.1U C6 4.7U C7 0.1U C8 22U 3.3VIN 3.3VOUT 1 2 3 4 STBY# 3.3VIN 3.3VOUT NC
RCLKEN
AUXOUT NC
15 14 13 12 11
AUXOUT
W83L351YG/YCG
NC 1.5VIN
1.5VIN 1.5VOUT
1.5VIN
1.5VOUT
5
SYSRST#
NC
1.5VOUT CPUSB# 9 PERST# CPPE# 10 GND 7
C9 0.1U
C10 4.7U
C11 0.1U
C12 22U
6
8
SY SRST#
CPPE# CPUSB# PERST#
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
4. INTERNAL BLOCK DIAGRAM
1.5VI N
SW1 SW4
1.5VOUT
3.3VIN
SW2 SW5
3.3VOUT
AUXIN
SW3 SW6
AUXOUT
CPUSB #
Detctor
Current Limit
CPPE #
Thermal protection
Control Logic STBY #
AUXIN POWER_GOOD_ALL
OC #
SHDN #
RCLKEN
GND
AUXIN
PERST # SYSRST #
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W83L351 Series
5. ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNIT
VI(3.3VIN) Input Voltage Logic Input/Output Voltage VO(3.3VOUT) Output Voltage VO(1.5VOUT) VO(AUXOUT) IO(3.3OUT) Output Current IO(1.5OUT) IO(AUXOUT) Operating Temperature Range Topt Human Body Mode Electrostatic discharge protection Machine Mode Latch-Up VI(1.5VIN) VI(AUXIN)
-0.3 to 6 -0.3 to 6 -0.3 to 6 -0.3 to 6 -0.3 to 6 -0.3 to 6 -0.3 to 6 Internally limited Internally limited Internally limited 0 to 70 2 200 100
V V V V V V V
kV V mA
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
6. RECOMMENDED OPERATING CONDITIONS
ITEM MIN MAX UNIT
VI(3.3VIN) Input Voltage VI(1.5VIN)
3.3VIN is only required for its respective functions 1.5VIN is only required for its respective functions
3 1.35 3 0 0 0
3.6 1.65 3.6 1.3 650 275 A mA mA V
VI(AUXIN) AUXIN is required for all circuit operations Continuous output current IO(3.3VOUT) IO(1.5VOUT) IO(AUXOUT) TJ=120
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W83L351 Series
7. ELECTRICAL CHARACTERISTICS
TA = 25, VI (3.3VIN) = VI (AUXIN) = 3.3 V, VI (1.5VIN) = 1.5 V, VI (SHDN#), VI (STBY#) = 3.3 V, VI (CPPE#) = VI (CPUSB#) = 0 V, VI (SYSRST) = 3.3 V, OC# and RCLKEN and PERST# are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.3VIN to 3.3VOUT with two switches on for dual Power switch resistance 1.5VIN to 1.5VOUT with two switches on for dual AUXIN to AUXOUT with two switches on for dual IOS Short - circuit output current Thermal Shutdown IOS(3.3VOUT) (steady-state value) IOS(1.5VOUT) (steady-state value) IOS(AUXOUT) (steady-state value) Trip point, TJ Hysteresis II(AUXIN) Normal operation II(3.3VIN) II(1.5VIN) II(AUXIN) II Total input quiescent current (Note: 1) Shutdown mode II(3.3VIN) II(1.5VIN) II(AUXIN) Standby mode (1) II(3.3VIN) II(1.5VIN) Standby mode (2) II(AUXIN) II(3.3VIN) II(1.5VIN)
TA = 25C, I = 1305 mA each TA = 70C, I = 1305 mA each TA = 25C, I = 660 mA each TA = 70C, I = 660 mA each TA = 25C, I = 285 mA each TA = 70C, I = 285 mA each 1.3 5 0.6 7 275 Rising temperature, not in over current condition Over current condition Outputs are unloaded (include CPPE# and CPUSB# logic pull-up currents) CPUSB# = CPPE# = 0 V SHDN# = 0 V (discharge FETs are on) (include CPPE# and CPUSB# logic pull-up currents and SHDN# pull-up current) CPUSB# = CPPE# = 0 V STBY# = 0 V (include CPPE# and CPUSB# logic pull-up currents and STBY# pull-up current) CPUSB# = CPPE# = 0 V 3.3VIN = 0 V (include CPPE# and CPUSB# logic pull-up currents)
90 105 90 110 110 126 1.7 1.1 400 155 130 10 140 10. 5 2.2 170 6 2.2 170 6 2.2 160 0 2.2 210 15 10 270 10 10 270 10 10 210 0.1 10 uA uA uA uA 2.5 1.3 600 A A mA m
Output powered into a short
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
Continued
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Standby mode (3) II(AUXIN) II(3.3VIN) II(1.5VIN)
II(AUXIN) II(3.3VIN) II(1.5VIN)
CPUSB# = CPPE# = 0 V 1.5VIN = 0 V (include CPPE# and CPUSB# logic pull-up currents) SHDN# = 3.3 V, CPUSB# = CPPE# = 3.3 V (no card present, discharge FETs are on);current measured at input pins, includes RCLKEN pull- up current SYSRST# = 3.6 V, sinking
160 6 0 22 0 0
210 10 0.1 50 50 50 uA uA
Ilkg(FWD) Forward leakage current
LOGIC SECTION (SYSRST, SHDN#, STBY#, PERST#, RCLKEN , OC#, CPUSB#, CPPE#) 0 10 17. 5 0 10 17. 5 0 10 10 17. 5 18 0 10 2 0.8 IO(RCLKEN) = 60 A 3.3VOUT falling AUXOUT falling 1.5VOUT falling 3.3VOUT, AUXOUT, 1.5VOUT falling 3.3VOUT, AUXOUT, or 1.5VOUT rising within tolerance 1 20 2.7 2.7 1.2 0.4 3 3 1.5 500 ns ms V 17. 5 uA 30 V V 30 30 uA uA 30 uA 30 uA I(SYSRS#) Input
SYSRST# = 0 V, sourcing SHDN# = 3.6 V, sinking
I(SHDN#) Logic input supply current
Input
SHDN# = 0 V, sourcing STBY# = 3.6 V, sinking
I(STBY#) I(RCLKEN ) I(CPUSB#) or I(CPPE#)
Input Input
STBY# = 0 V, sourcing RCLKEN = 0 V, sourcing CPUSB# or CPPE# = 0 V, sinking CPUSB# or CPPE# = 3.6 V, sourcing
inputs
Logic input voltage RCLKEN output low voltage
High level Low level Output
PERST# assertion threshold of output voltage (PERST# asserted when any output voltage falls below the threshold) PERST# assertion delay from output voltage PERST# de-assertion output voltage delay from
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W83L351 Series
Continued
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PERST# assertion SYSRST#
delay
from
Max time from SYSRST asserted 3.3VOUT, AUXOUT, or 1.5VOUT falling out of tolerance or triggered by SYSRST# IO(PERST#) = 500 A IO(OC#) = 2 mA Falling into or out of an over current condition 100
25
500
ns
tW(PERST#) PERST# minimum pulse width PERST# output low voltage PERST# output high voltage OC# output low voltage OC# deglitch
UNDERVOLTAGE LOCKOUT (UVLO)
340
us
0.4 2.4 0.4 20
V V V ms
3.3VIN UVLO
3.3VIN level, below which 3.3VIN and 1.5VIN switches are off 1.5VIN level, below which 3.3VIN and 1.5VIN switches are off AUXIN level, below which all switches are off
2.6
2.9 V
1.5VIN UVLO AUXIN UVLO UVLO hysteresis
1.0 2.6 100
1.25 2.9
mV
Note 1: In the Shutdown mode or the Standby mode (1), the AUXIN quiescent current includes a normal operation current, SHDN# or STBY# internal pull-up current and RCLKEN internal pull-up current. In the Standby modes (2) & (3), the AUXIN quiescent current includes a normal operation current and a RCLKEN internal-up current.
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
8. SWITCHING CHARACTERISTICS
TA = 25, VI (3.3VIN) = VI (AUXIN) = 3.3 V, VI (1.5VIN) = 1.5 V, VI (SHDN#), VI (STBY#) = 3.3 V, VI (CPPE#) = VI (CPUSB#) = 0 V, VI (SYSRST) = 3.3 V, OC# and RCLKEN and PERST# are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
3.3VIN to 3.3VOUT AUXIN to AUXOUT 1.5VIN to 1.5VOUT
TEST CONDITIONS
CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A CL(3.3VOUT)=100uF, RL=VI(3.3VIN)/1A CL(AUXVOUT)=100uF, RL=VI(AUXININ)/0.250A CL(1.5VOUT)=100uF, RL=VI(1.5VIN)/0.500A CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A CL(3.3VOUT)=20uF, IO(3.3VOUT)=0A CL(AUXVOUT)=20uF, IO(AUXOUT)=0A CL(1.5VOUT)=20uF, IO(1.5VOUT)=0A CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A CL(3.3VOUT)=100uF, RL=VI(3.3VIN)/1A CL(AUXVOUT)=100uF, RL=VI(AUXININ)/0.250A CL(1.5VOUT)=100uF, RL=VI(1.5VIN)/0.500A CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A CL(3.3VOUT)=100uF, RL=VI(3.3VIN)/1A CL(AUXVOUT)=100uF, RL=VI(AUXININ)/0.250A CL(1.5VOUT)=100uF, RL=VI(1.5VIN)/0.500A
MIN
0.1 0.1 0.1 0.1 0.1 0.1 10 10 10 5 5 5 10 10 10 0.1 0.1 0.1 0.1
0.1 0.1 0.1 0.1 0.1
TYP
MAX
6 6 6 6 6 6 150 150 150 30 30 30 150 150 150 3 3 3 6
6 6 6 6 6
UNIT
tr Output rise times
3.3VIN to 3.3VOUT AUXIN to AUXOUT 1.5VIN to 1.5VOUT
ms
tf Output fall times when card removed (both CPUSB# and CPPE# deasserted)
3.3VIN to 3.3VOUT AUXIN to AUXOUT 1.5VIN to 1.5VOUT 3.3VIN to 3.3VOUT AUXIN to AUXOUT 1.5VIN to 1.5VOUT 3.3VIN to 3.3VOUT AUXIN to AUXOUT 1.5VIN to 1.5VOUT 3.3VIN to 3.3VOUT AUXIN to AUXOUT 1.5VIN to 1.5VOUT 3.3VIN to 3.3VOUT AUXIN to AUXOUT
us
ms
tf Output fall times when SHDN# asserted (card is present)
us
ms
Tpd(on) Turn on propagation delay
1.5VIN to 1.5VOUT 3.3VIN to 3.3VOUT AUXIN to AUXOUT 1.5VIN to 1.5VOUT
ms
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W83L351 Series
9. FUNCTIONAL TRUTH TABLES
Truth Table for Voltage Outputs
VOLTAGES INPUTS (1) AUXIN 3.3VIN 1.5VIN LOGIC INPUTS SHDN# STBY# CP#
(4)
VOLTAGE OUTPUTS(2) AUXOUT 3.3VOUT 1.5VOUT
MODE(3)
Off On On On On On On On On (1) (2) (3) (4) (5) (6) (7)
X Off On On X X On On Off On
X Off On On X X On On Off On
X 1 1 1 0 1 1 1 1
X 1 0 0 X X 0 1 1
X X 0 X X 1 0 0 0
Off Off Off Off GND GND On On On
Off Off Off Off GND GND Off Off On
Off Off Off Off GND GND Off Off On
Off Off Off(5) Off(6) Shutdown No Card Standby Standby(7) Card Inserted
For input voltages, On means the respective input voltage is higher than its turn on threshold voltage; otherwise, the voltage is Off (for AUX input, Off means the voltage is close to zero volt). For output voltages, On means the respective power switch is turned on so the input voltage is connected to the output; Off means the power switch and its output discharge FET are both off; Gnd means the power switch is off but the output discharge FET is on so the voltage on the output is pulled down to 0 V. Mode assigns each set of input conditions and respective output voltage results to a different name. These modes are referred to as input conditions in the following Truth Table for Logic Outputs. CP# = CPUSB# and CPPE# equal to 1 when both CPUSB# and CPPE# signals are logic high, or equal to 0 when either CPUSB# or CPPE# is low. STBY# is asserted (logic low) prior to the card being present. STBY# is asserted (logic low) prior to the voltage inputs being present. The card is inserted prior to the removal of the Primary or Secondary power (either 3.3VIN or 1.5VIN or both) at the input of the ExpressCard power switch, then only the primary and secondary power (both 3.3VOUT and 1.5VOUT) are removed and the auxiliary power is sent to the ExpressCard slot.
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
Truth Table for Logic Outputs
INPUT CONDITIONS MODE SYSRST# RCLKEN
(1)
LOGIC OUTPUTS PERST# RCLKEN (2)
Off Shutdown No Card Standby 0 Card Inserted 0 1 1 (1) (2) Hi - Z 0 Hi - Z 0 0 0 1 0 1 0 1 0 X X 0 0
RCLKEN as a logic input in this column. RCLKEN is an I/O pin and it can be driven low externally, left open, or connected to high-impedance terminals, such as the gate of a MOSFET. It must not be driven high externally. RCLKEN as a logic output in this column.
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W83L351 Series
10. TYPICAL OPERATING WAVEFORMS
CH1 CPPE# CH2 3.3VOUT CH3 1.5VOUT CH4 AUXOUT Fig.1 Output Voltage When Card Is Inserted
CH1 3.3VOUT CH2 RCLKEN CH3 PERST# Fig.2 RCLKEN and PERST# Voltage During Power Up
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
CH1 AUXOUT CH2 RCLKEN CH3 PERST# Fig.3 RCLKEN and PERST# Voltage During Power Down
CH1 SYSRST# CH2 PERST# Fig.4 PERST# Asserted by SYSRST# When Power Is On
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W83L351 Series
CH1 SYSRST# CH2 PERST# Fig.5 PERST# De-Asserted by SYSRST# When Power Is On
CH1 3.3VIN CH2 3.3VOUT CH3 1.5VOUT CH4 AUXOUT Fig.6 Output Voltage When 3.3VIN Is Removed
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
CH1 1.5VIN CH2 3.3VOUT CH3 1.5VOUT CH4 AUXOUT Fig.7 Output Voltage When 1.5VIN Is Removed
CH1 OC# CH2 AUXOUT
Fig.8 OC# Response When AUXOUT Power Into A Short
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W83L351 Series
CH1 OC# CH2 3.3VOUT Fig.9 OC# Response When 3.3VOUT Power Into A Short
CH1 OC# CH2 1.5VOUT Fig.10 OC# Response When 1.5VOUT Power Into A Short
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W83L351 Series
11. EXPRESSCARD TIMING DIAGRAMS
Tpd Min Max Units a b c d e 100 1 20 System dependent 100 10 us ms us ms
Fig.11 Card Present Before Host Power (Note.1)
Tpd Min Max Units a b c 1 100 10 20 us ms ms
Fig.12 Host Power Is On Prior To Card Insertion (Note.2)
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W83L351 Series
Fig.13 Host System In Standby Prior to Card Insertion
Tpd Min a b c d
Max Units
System dependent Load dependent 500 500 ns ns
Fig.14 Host Controlled Power Down (Note.3)
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
Tpd Min Max Units a b c d e System dependent System dependent Load dependent 500 500 ns ns
Fig.15 Controlled Power Down When SHDN# Asserted (Note.4)
Tpd Min Max Units a b c Load dependent 500 500 ns ns
Fig.16 Surprise Card Removal
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W83L351 Series
Note.1: According to the electrical specifications of ExpressCard Standard, the minimum propagation delay time of e (Power stable to PERST# inactive) is 1ms. Note.2: RCLKEN could be treated as a power good signal when card power is over 86% of nominal voltage. Note.3: The propagation delay time of c is SYSRST# assertion to PERST# assertion. The propagation delay time of d is card power is under 86% of nominal voltage to RCLKEN de-assertion. Note 4: RCLEKN de-assertion is prior to PERST# assertion when card power lost in any situation.
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
12. PACKAGE DIMENSION W83L351G - TSSOP20
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W83L351 Series
W83L351YG - QFN20, Thermal Pad Dimension: 2.0mm X 2.0mm
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
W83L351YCG - QFN20, Thermal Pad Dimension: 2.7mm X 2.7mm
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W83L351 Series
Taping Specification
20 Pin TSSOP Package
20 Pin QFN Package
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
13. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE SUPPLIED AS PRODUCTION FLOW
W83L351G
20PIN TSSOP (Pb-free package) 20PIN QFN (Pb-free package)
E Shape: 74 units/Tube T Shape: 2,500 units/T&R E Shape: 490 units/Tray
Commercial, 0 to +70 Commercial, 0 to +70
W83L351YG
Thermal Pad Size: 2.0X2.0 T Shape: 4,000 units/T&R 20PIN QFN (Pb-free package) E Shape: 490 units/Tray
W83L351YCG
Commercial, 0 to +70
Thermal Pad Size: 2.7X2.7 T Shape: 4,000 units/T&R
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W83L351 Series
14. TOP MARKING SPECIFICATION
W83L351G 212345678 606XARA
Left line: Winbond logo 1st line: W83L351G - the part number 2nd line: Chip lot no 3rd line: Tracking code 606 X ARA 606: Packages assembled in Year 06', week 06 X: Assembly house ID ARA: The IC version
Winbond 351YG 636XARB
Winbond 351YCG 636XARB
1st line: Winbond - company name 2nd line: 351YG/351YCG - the part number 3rd line: Tracking code 636 X ARB 636: Packages assembled in Year 06', week 36 X: Assembly house ID ARB: The IC version
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Publication Date: July 5, 2007 Revision 1.10
W83L351 Series
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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